The present invention relates to a semiconductor memory device fabricated on a semiconductor substrate and more particularly to a word line drive circuit thereof for selectively driving word lines.
Semiconductor memories are formed by arranging a large number of memory cells in a matrix form of rows and columns and memory cells are coupled to word lines arranged in rows and digit lines in columns. A read operation is performed by selecting one of the word lines The memory cells coupled to the selected word line produce read-out signals on the respective digit lines. While, in a write operation, one of the word lines is selected and the memory cells coupled to the selected memory cells are enabled to take therein the levels of the respective digit lines to which write data signals are applied.
In a recent tendency, the number of memory cells, that is memory capacity, is remarkably increased, and 256 k-bit and 1 M-bit memory devices are now commercially available
Accompanied by the increase in the memory capacity, the number of word lines is greatly increased and the number of address signals for selecting each word line is also increased. Therefore, the number of transistors of each decoding unit for each word line is thus increased and hence it has become difficult to arrange each decoding unit with a minimum pitch of the word lines. Under such circumstance, it has been proposed such technique that a plurality of word lines are classified into a plurality of word line groups and a first decoder for selecting one of the word lines groups and a second decoder for selecting one of the word lines of the selected word line group are employed. According to the above technique, a transfer gate field effect transistor is coupled between each word line and the relevant output of the first decoder for selectively transferring the output of the first decoder to the relevant word line under control of the second decoder.
However, as is well known in the art, the potential applied to the selected word line is lower than the potential of a power voltage (Vcc) by a threshold voltage (Vth) of the transfer gate transistor.
Therefore, it is difficult to raise the potential of the selected word line to the power voltage Vcc for high speed operation and maximum utilization of the power voltage.
Moreover, the capacitances of the respective word lines are also increased in proportion to the increase in the memory capacity, so that a time constant of the word line is increased in its longitudinal direction, causing low speed driving of the word line.